The present invention generally relates to a process for forming a patterned copper layer, and the patterned copper layer formed. More particularly, the present invention is directed to a technique which can be applied for forming copper interconnections and/or wirings of semiconductor devices (for example, a technique for forming integrated circuit devices having patterned copper interconnections and/or wirings, including multi-level interconnections and/or wirings), and the semiconductor device (integrated circuit device) produced.
As a result of the increase in high-speed operation, and increased integration, of large scale integrated circuits (LSI's), there has been a demand for material for the interconnections and for the wirings, in such LSI's, which are lower in resistance and higher in reliability than aluminum, which has previously been employed for the interconnections and wirings.
As a material which satisfies these requirements of decreased resistance and increased reliability, copper (having a resistivity of 1.56 .mu..OMEGA.-cm) has attracted special interest recently. A recently developed process for forming copper interconnections is discussed in Extended Abstracts (The 47th Meeting, September 1986), 30 p-N-12, page 513, the Japan Society of Applied Physics. According to this process, a copper film is formed on a titanium nitride (TiN) film, and another TiN film is formed on the copper film; thereafter, a photoresist pattern having a predetermined configuration is formed on the upper TiN film. With this photoresist pattern used as a mask, the upper TiN film is etched by reactive ion etching (RIE), and the photoresist pattern is then removed. Next, with the etched TiN film used as a mask, the copper film is etched by ion milling to form the copper interconnection. In the disclosed technique, the TiN underlayer was provided beneath the copper as a diffusion barrier, to prevent diffusion of the copper into the substrate (of silicon or silicon oxide).
The product formed by such recently developed process, including an ion milling of the copper layer, is shown in FIG. 6. Thus, FIG. 6 shows a TiN barrier layer 63 between the substrate (of SiO.sub.2) 64 and patterned copper layer 62, with a TiN layer 61, utilized as a mask in etching the copper to provide patterned copper layer 62, being also shown in this FIG. 6. As is clear from FIG. 6, the profile of the pattern is tapered, with .theta..sub.1 being less than 90.degree. (for example 60.degree.-70.degree.). Moreover, due to the tapered profile of the copper layer, the minimum space between interconnections (that is, the space shown in FIG. 6), as well as the minimum line width, is approximately 3 .mu.m. In addition, through use of the ion milling for etching the copper, the substrate will be etched (as shown by reference character 66 in FIG. 6), for example, to a thickness of at least 1,000.ANG. (0.1 .mu.m).
In the foregoing recently developed process, ion milling is utilized to etch the copper; previous to use of such ion milling to etch the copper, it had been difficult to etch copper utilized for interconnections and/or wiring layers of semiconductor devices. Moreover, in the above-discussed recently developed process, TiN is utilized between the photoresist and copper due to poor selectivity, for etching, of the photoresist over copper, and poor selectivity, for etching, of the photoresist over the substrate material (silicon oxide or silicon) on which the copper layer is formed. In this recently developed process, ion milling is used only to etch the copper; conventional photolithography is utilized to form the pattern in the photoresist, with reactive ion etching, known in the art, being used to etch the TiN.